(1) Field of the Invention
The present invention generally relates to the field of communication networks. More particularly the present invention relates to alignment of data in communications networks.
(2) Background
Communication networks typically use communication interfaces (hereinafter referred to as xe2x80x9cline cardsxe2x80x9d) to transmit/receive data to/from communication lines. Data may also be transmitted from ingress line cards via serial links to egress line cards. On its way to the egress line cards, data is switched by a switch fabric. FIG. 1 illustrates a communication network 100 that includes ingress line cards 102 and 104 that communicate with egress line cards 108 and 110 via switch fabric 106 (hereinafter referred to as xe2x80x9cswitch devicexe2x80x9d). Switch device 106 includes switch planes (hereinafter referred to as xe2x80x9cswitch cardsxe2x80x9d) 113 and 114 by way of which data, transmitted by ingress line cards 102 and 104, is switched to egress line cards 108 and 110.
Each ingress line card may make a request for transmitting data, via switch device 106, to an egress card. A switch card, such as switch card 113 for example, decides which request from an ingress line card may be granted, so data may be transmitted from the line card to the respective switch card. When an ingress line card that made a request to a switch card receives a grant back from the switch card, it starts transmitting data to the switch card. Data is serially transmitted by each line card in the form of units of data (hereinafter referred to as xe2x80x9ccellsxe2x80x9d) to switch device 106 through an associated transceiver, such as transceiver 120, and channels 112 and 114. For simplification, FIG. 1 illustrates two ingress line cards 102 and 104, two egress line cards 108 and 110, and two switch cards 113 and 114. However, the following discussion pertains to network systems that may include any number of line cards and switch cards.
FIG. 2 illustrates a chassis 200 of a communication network such as the communication network described above in connection with the illustration of FIG. 1. Chassis 200 includes a switch device 206 with a switch card 216 and a plurality of line card slots 202, 204, 214, 216, and 218 that may be positioned on each side of switch device 206. Various line cards (not shown) may be plugged into the plurality of line card slots shown in the figure. Traces 208 and 210 couple the line card slots and thereby their associated line cards to switch card 216. As line cards slots 202 and 204 are located in the chassis at different positions with respect to switch device 206, the length of each trace may vary from one line card slot to another line card slot. For example, trace 210 is shorter than trace 208 as line card slot 204 is positioned closer to switch card 216 than line card slot 202. The differences in the lengths of various traces may cause problems at the destination where the cells may arrive misalginedxe2x80x94i.e., at substantially different bit times. Cells departing from the source aligned to a specific clock count, may arrive at the destination misaligned. Because serial data is transmitted at high frequency, within the Gigahertz (GHz) range, even the slightest differences between the lengths of various traces may cause.data flowing through these traces to arrive at the destination misalgined. However, the cells transmitted through different channels are expected to arrive at the destination at a substantially same time so that these cells may be aligned and processed at the destination at a substantially same time. The destination may either be the switch cards, when data is sent out by the line cards, or the line cards, when data is sent out by the switch cards.
Misalignment may also be caused by other factors. These factors include parallel/serial transceiver latency, such as transmit or receive latencies, temperature differences at different parts of the system, different loading for different channels, crosstalk, etc. Transceiver latency may be transmit latency (TX Latency) or receive latency (RX Latency). xe2x80x9cTX latencyxe2x80x9d may be defined as the time that takes a cell to pass from the input of a transceiver""s transmitter to the output of the transceiver""s transmitter. xe2x80x9cRX latencyxe2x80x9d may be defined as the time that takes a cell to pass from the input of the transceiver""s receiver to the output of the transceiver""s receiver. TX and RX latencies are mainly caused by the analog recovery circuitry of transceivers. These latencies may not be quantified by a predictable number and differ from transceiver to transceiver. Traces may also be subject to cross talk which may cause data flowing through different channels to arrive at the destination at different times. Loading may also affect the arrival time of data flowing through different channels as each trace has a different loading.
A communication interface is described to align at a destination data transmitted through different channels, before that data is read out. The communication interface includes a receiver with a plurality of buffers. Each buffer is coupled to a corresponding channel to receive data therethrough. The communication interface also includes.a control circuit coupled to the plurality of buffers. The control circuit enables a reading of data from the plurality of buffers when each of the plurality of buffers has received at least one unit of data.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.